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| KM23V4000D(E)TY/KM23S4000D(E)TY 4M-Bit (512Kx8) CMOS MASK ROM FEATURES * 524,288 x 8 bit organization * Fast access time 3.3V Operation : 100ns(Max.) 3.0V Operation : 120ns(Max.) 2.5V Operation : 250ns(Max.) * Supply voltage KM23V4000D(E)TY : single +3.0V/ single +3.3V KM23S4000D(E)TY : single +2.5V * Current consumption Operating : 25mA(Max.) Standby : 30A(Max.) * Fully static operation * All inputs and outputs TTL compatible * Three state outputs * Package -. KM23V(S)4000D(E)TY : 32-TSOP1-0820 CMOS MASK ROM GENERAL DESCRIPTION The KM23V4000D(E)TY and KM23S4000D(E)TY are fully static mask programmable ROM organized 524,288 x 8 bit. It is fabricated using silicon gate CMOS process technoiogy. This device operates with low power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The KM23V4000D(E)TY and KM23S4000D(E)TY are packaged in a 32-TSOP1. FUNCTIONAL BLOCK DIAGRAM A18 X BUFFERS AND DECODER MEMORY CELL MATRIX (524,288x8) PRODUCT INFORMATION Product Operating Temp Range 0C~70C . . . . . . . . A0 Y BUFFERS AND DECODER SENSE AMP. BUFFERS CE OE CONTROL LOGIC Pin Name A0 - A18 Q0 - Q7 CE OE VCC VSS N.C w w w .D t a ... S a Q7 e h A11 A9 A8 A13 A14 A17 N.C VCC A18 A16 #1 KM23V4000DTY KM23S4000DTY t e U 4 .c m o 2.5V Vcc Range (Typical) 3.3V/3.0V Speed (ns) 100/120 250 100/120 250 KM23V4000DETY KM23S4000DETY -20C~85C 3.3V/3.0V 2.5V PIN CONFIGURATION #32 OE A10 CE Q7 Q6 Q5 Q4 Q0 32-TSOP1 Q3 VSS Q2 Q1 Q0 Pin Function A15 A12 A7 A6 A5 A4 #16 #17 Address Inputs Data Outputs Chip Enable Output Enable Power Ground No Connection KM23V4000D(E)TY KM23S4000D(E)TY w w w .D at a he S et 4U A1 A2 A3 A0 . om c KM23V4000D(E)TY/KM23S4000D(E)TY ABSOLUTE MAXIMUM RATINGS Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Symbol VIN TBIAS TSTG Rating -0.3 to +4.5 -10 to +85 -55 to +150 0 to +70 Operating Temperature TA -20 to +85 CMOS MASK ROM Unit V C C C C Remark KM23V4000DTY KM23S4000DTY KM23V4000DETY KM23S4000DETY NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS) Item Symbol VCC VSS Min 2.7/3.0 2.3 0 Typ 3.0/3.3 2.5 0 Max 3.3/3.6 2.7 0 Unit V V V Supply Voltage DC CHARACTERISTICS Parameter Symbol Test Conditions VCC=3.30.3V Operating Current ICC CE=OE=VIL, all outputs open VCC=3.00.3V VCC=2.50.2V Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs VIL ISB1 ISB2 ILI ILO VIH KM23V4000D(E)TY KM23S4000D(E)TY KM23V4000D(E)TY KM23S4000D(E)TY VOL IOH=-400A IOH=-400A IOL=2.1mA CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC Min 2.0 -0.3 -0.3 2.4 2.0 Max 25 20 15 500 30 10 10 VCC+0.3 0.6 0.4 0.4 Unit mA mA mA A A A A V V V V V V Output High Voltage Level Output Low Voltage Level VOH NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. MODE SELECTION CE H L OE X H L Mode Standby Operating Operating Data High-Z High-Z Dout Power Standby Active Active KM23V4000D(E)TY/KM23S4000D(E)TY CAPACITANCE(TA=25C, f=1.0MHz) Item Output Capacitance Input Capacitance Symbol COUT CIN Test Conditions VOUT=0V VIN=0V MIN - CMOS MASK ROM Max 10 10 Unit pF pF NOTE : Capacitance is periodically sampled and not 100% tested. AC CHARACTERISTICS(VCC=3.3V/3.0V0.3V / VCC=2.5V0.2V, unless otherwise noted.) TEST CONDITIONS Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads Value 0.45V to 2.4V (at VCC=3.3V/3.0V) 0.4V to 2.2V (at VCC=2.5V) 10ns 1.5V (at VCC=3.3V/3.0V) 1.1V (at VCC=2.5V) 1 TTL Gate and CL=100pF READ CYCLE Item Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change Symbol tRC tACE tAA tOE tDF tOH 0 VCC=3.3V0.3V Min 100 100 100 50 20 0 Max VCC=3.0V0.3V Min 120 120 120 60 20 0 Max VCC=2.5V0.2V Min 250 250 250 110 50 Max Unit ns ns ns ns ns ns TIMING DIAGRAM READ ADD ADD1 tRC tACE ADD2 tDF(Note) CE tOE OE tOH DOUT VALID DATA VALID DATA tAA NOTE : tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level. KM23V4000D(E)TY/KM23S4000D(E)TY PACKAGE DIMENSIONS 32-TSOP1-0820 +0.10 0.20 -0.05 +0.004 0.008 -0.002 CMOS MASK ROM (Unit : mm/inch) 20.000.20 0.7870.008 #32 ( 8.40 0.331MAX 8.00 0.315 0.25 ) 0.010 #1 0.50 0.0197 #16 #17 1.000.10 0.0390.004 1.20 0.047MAX +0.10 -0.05 0.006+0.004 -0.002 0.05 0.002 MIN 0.25 0.010 TYP 18.400.10 0.7240.004 0.15 0~8 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 0.10 MAX 0.004 MAX |
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